S.M. Chung, M.D. Shieh, and C.K. Chiueh, “FETCH: A Cloud-Native Searchable Encryption Scheme Enabling Efficient Pattern Search on Encrypted Data within Cloud Services,” accepted to International Journal of Communicatio System, 2019.
2018
J.H. Ye, and M.D. Shieh, 2018, May, "Low-Complexity VLSI Design of Large Integer Multipliers for Fully Homomorphic Encryption," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no.9, pp. 1727-1736.
2015
J.S. Lin, Y.T. Hwang, S.H. Fang, and M.D. Shieh, 2015, October, “Low-complexity High-throughput QR Decomposition Design for MIMO Systems,” IEEE Transactions on VLSI Systems, vol. 23, no. 10, pp. 2342-2346.
H.F. Luo, Y.J. Liu, and M.D. Shieh, 2015, October, “Efficient Memory Addressing Algorithms for FFT Processor Design,” IEEE Transactions on VLSI Systems, vol. 23, no. 10, pp. 2162-2172.
D.W. Yang, L.C. Chu, C.W. Chen, J. Wang, and M.D. Shieh, 2015, June, “Depth-reliability-based Stereo Matching Algorithm and its VLSI Architecture Design,” IEEE Transactions on Circuit and System for Video Technology, vol. 25, no. 6, pp. 1038-1050.
2014
W.C. Lin, J.H. Ye and M.D. Shieh, 2014, February, “Scalable Montgomery Modular Multiplication Architecture with Low Latency and Low Memory Bandwidth Requirement," IEEE Transactions on Computers, vol. 63, no. 2, pp 475-483.
2013
S.H. Fang, J.Y. Chen, M.D. Shieh and J.S. Lin, 2013, December, “Subspace-Based Blind Channel Estimation by Separating Real and Imaginary Symbols for Cyclic-Prefixed Single-Carrier Systems,” IEEE Transactions on Broadcasting, vol. 59, no. 4, pp 698-704.
Y.F. Chou, D. M. Kwai, M.D. Shieh and C.W. Wu, 2013, September, “Reactivation of Spares for Off-Chip Memory Repair After Die Stacking in a 3-D IC With TSVs,” IEEE Transactions on Circuits and Systems I, vol. 60, no. 9, pp 2343-2351.
C.C Lo, C.W. Hsu and M.D. Shieh, 2013, April, “Low-complexity multi-standard variable length coding decoder using tree-based partition and classification,” IET Image Processing, vol. 7, Iss. 3, pp 185-190.
Y.K. Lu and M.D. Shieh, 2013, January, “Initial settings of Berlekamp-Massey algorithm for efficient hardware implementation,” Electronics Letters, vol. 49, no. 3, pp. 190-191.
2012
S.H. Fang, J.Y. Chen, M.D. Shieh and J.S. Lin, 2012, November, “Blind Channel Estimation for Cyclic Prefix-free Orthogonal Frequency-division Multiplexing Systems with Particular Input Symbols,” IET Communications, vol. 6, Iss. 16, pp. 2654-2660.
S.F. Lei, C.C. Lo, C.C. Kuo and M.D. Shieh, 2012, June, “Low-power context-based adaptive binary arithmetic encoder using an embedded cache,” IET Image Processing, vol. 6, Iss. 4, pp. 309-317.
M.D. Shieh, S.H. Fang, S.C. Tang and D.W. Yang, 2012, February, “Low-complexity Memory Access Architectures for Quasi-cyclic LDPC Decoders,” IEICE Transactions on Information and Systems, vol. E95.D, no. 2, pp. 549-557.
2011
M.D. Shieh and Y.K. Lu, 2011, August, "Design and Implementation of a Low-Complexity Reed-Solomon Decoder for Optical Communication Systems," IEICE Transactions on Information and Systems, vol. E94.D, no. 8, pp. 1557-1564.
C.L. Wey, S.Y. Lin, P.Y. Tsai and M.D. Shieh, 2011, July, “Reconfigurable Homogenous Multi-Core FFT Processor Architectures for Hybrid SISO/MIMO OFDM Wireless Communications,” IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, vol. E94A, no. 7, pp 1530-1539.
W.C. Lin, M.D. Shieh and C.M. Wu, 2011, May, "Design of High-Speed Iterative Dividers in GF(2m)," Journal of Information Science and Engineering, vol. 27, no. 3, pp. 953-967.
2010
S.Y. Lin, C.L. Wey and M.D. Shieh, 2010, November, “Low-cost FFT processor for DVB-T2 applications,” IEEE Transactions on Consumer Electronics, vol. 56, no. 4, pp 2072-2079.
C.C. Lo, S.T. Tsai and M.D. Shieh, 2010, August, "Reconfigurable Architecture for Entropy Decoding and Inverse Transform in H.264," IEEE Transactions on Consumer Electronics, vol. 56, no. 3, pp. 1670-1676.
M.D. Shieh and W.C. Lin, 2010, August, "Word-Based Montgomery Modular Multiplication Algorithm for Low-Latency Scalable Architectures," IEEE Transactions on Computers, vol. 59, no. 8, pp. 1145-1151.
J.H. Chen, M.D. Shieh and W.C. Lin, 2010, August, "A High-Performance Unified-Field Reconfigurable Cryptographic Processor," IEEE Transactions on VLSI Systems, vol. 18, no. 8. pp.1145-1158.
Y.K. Lu and M.D. Shieh, 2010, July, “High-Speed Low-Complexity Architecture for Reed-Solomon Decoders,” IEICE Transactions on Information and Systems, vol. E93.D, no. 7, pp. 1824-1831.
S.H. Fang, J.Y. Chen, M.D. Shieh and J.S. Lin, 2010, January, “Blind Channel Estimation for SIMO-OFDM Systems without Cyclic Prefix,” IEICE Transaction on Fundamentals, vol. E93.A, no. 1, pp. 339-343.
2009
M.D. Shieh, Y.K. Lu and S. M. Chung, 2009, December, “Efficient Reed-Solomon Decoder Design for Multi-Mode Applications,” Journal of Electrical Engineering, vol.16, no.6, pp.503-516.
M.D. Shieh, J.H. Chen, W.C. Lin and H.H. Wu, 2009, September, “A New Algorithm for High-Speed Modular Multiplication Design,” IEEE Transaction on Circuits and Systems I, vol.55, no.11, pp.3430-3437.
M.D. Shieh, J.H. Chen, W.C. Lin and C.M. Wu, 2009, September, “An Efficient Multiplier/Divider Design for Elliptic Curve Cryptosystem over GF(2m),” Journal of Information Science and Engineering, vol.25, no.5, pp.1555-1573.
M.D. Shieh, T.P. Wang and D.W. Yang, 2009, April, “Low-Power Register-Exchange Survivor Memory Architectures for Viterbi Decoders,” IET Circuits, Devices & Systems , vol. 3, no. 2, pp. 83-90.
C.C. Lo, Y.J. Zeng and M.D. Shieh, 2009, April, “Design of A High-Throughput CABAC Encoder,” IEICE Transaction on Information and Systems, vol. E92.D, no. 4, pp. 681-688.
2008
C.L. Wey, M.D. Shieh and S.Y. Lin, 2008, December, “Algorithms of Finding the First Two Minimum Values and Their Hardware Implementation,” IEEE Transactions on Circuits and Systems I, vol.55, no.11, pp.3430-3437.
M.D. Shieh, T.P. Wang and C.M. Wu, 2008, September, “Reducing Interconnect Complexity for Efficient Path Metric Memory Management in Viterbi Decoders,” IEICE Transactions on Information and Systems , vol. E91-D, no. 9, pp. 2300-2311.
M.D. Shieh, J.H. Chen, H.H. Wu and W.C. Lin, 2008, September, “A New Modular Exponentiation Architecture for Efficient Design of RSA Cryptosystem,” IEEE Transactions on VLSI Systems, vol. 16, pp. 1151-1161.
2006
M.D. Shieh, J.H. Chen and C.M. Wu, 2006, February, “High-Speed Design of Montgomery Inverse Algorithm over GF(2m),” IEICE Transactions on Fundamentals, vol. E89-A, no. 2, pp. 559-565.
2005
C.M. Wu, M.D. Shieh, C.H. Wu, Y.T. Hwang and J.H. Chen, 2005, April, “VLSI Architectural Design Tradeoffs for Sliding-Window Log-MAP Decoders,” IEEE Transactions on VLSI Systems, vol. 13, no. 4, pp. 439-447.
2004
C.H. Wu, C.M. Wu, M.D. Shieh and Y.T. Hwang, 2004, March, “High-Speed, Low-Complexity Systolic Designs of Novel Iterative Division Algorithms in GF(2m),” IEEE Transactions on Computers, vol. 53, no. 3, pp. 375-380.
2003
C.M. Wu, M.D. Shieh, M.H. Hu and M.C. Lee, 2003, November, “Design and Implementation of Punctured Viterbi Decoder with Full Decoding Capability for DAB System,” Journal of Chinese Institute of Electrical Engineering, vol. 10, no. 4, pp. 331-343.
C.M. Wu, M.D. Shieh and C.H. Wu, 2003, November, “Exploring General Memory Structures in Turbo Decoders Using Sliding Window MAP Algorithm,” IEICE Transactions on Communications, vol. E86-B, no. 11, pp. 3163-3173.
M.D. Shieh, C.M. Wu, Y.T. Hwang, H.F. Lo and M.H. Hu, 2003, August “Realization of Area-Efficient FFT Processors,” Journal of Chinese Institute of Electrical Engineering, vol. 10, no. 3, pp. 269-280.
2002
C.H. Wu, C.M. Wu, M.D. Shieh and Y.T. Hwang, 2002, May, “Novel Algorithms and VLSI Design for Division over GF(2m),” IEICE Transactions on Fundamentals, vol. E85-A, no. 5, pp. 1129-1139.
C.H. Wu, M.D. Shieh, J.Y. Huang, H.W. Chang and C.M. Wu, 2002, March, “Comparative Study of Iterative Turbo Decoding Algorithms,” Journal of Science and Technology, vol. 11, no. 2, pp.91-99.
2001
M.D. Shieh, M.H. Sheu, C.H. Chen and H.F. Lo, 2001, May, “A Systematic Approach for Parallel CRC Computations,” Journal of Information Science and Engineering, pp. 445-461.
1999
M.D. Shieh, C.M. Wu, H.H. Chou, M.H. Chen and C.L. Liu, 1999, August, “Design and Implementation of a DAB Channel Decoder,” IEEE Transactions on Consumer Electronics, vol. 45, no. 3, pp. 553-562.
M.D. Shieh, H.H. Chou and C.M. Wu, 1999, May, “Design and Implementation of Deinterleaver and L3 Interface for DAB System,” CCL Technical Journal (電腦與通訊月刊), vol. 79, pp. 38-44.
M.D. Shieh, C.M. Wu, and H.H., Chou, 1999, May, “Design of the Variable-rate Punctured Viterbi Decoder for DAB System,” CCL Technical Journal (電腦與通訊月刊), vol. 79, pp. 30-37.
1998
C.L. Wey and M.D. Shieh, 1998, September, “Design of a High-Speed Square Generator,” IEEE Transactions on Computers, vol. 47, no. 9, pp. 1021-1026.
1993
M.D. Shieh, C.L. Wey, and P.D. Fisher, 1993, November, “Fault Effects in Asynchronous Sequential Logic Circuits,” IEE Proceedings-E Computers and Digital Techniques, vol.140, pp.327-332.
Conference
2019
H.C. Hsiao, C.W. Chen, J. Wang, M.D. Shieh, P.Y. Chen, 2019, April, "Architecture-aware Memory Access Scheduling for High-throughput Cascaded Classifiers," accepted, 2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems.
J.N. Ji and M.D. Shieh, 2019, May, "Efficient Comparison and Swap on Fully Homomorphic Encrypted Data," accepted, 2019 IEEE International Symposium on Circuits and Systems.
2018
J.H. Ye, S.Q. Chen and M.D. Shieh, 2018, May, “Minimizing ESOP Expressions for Fully Homomorphic Encryption,” accepted, 2018 IEEE International Symposium on Circuits and Systems.
C.W. Chen, W.Y. Hsiao, T.Y. Lin, J. Wang and M.D. Shieh, 2018, May, “Fast Keyframe Selection and Switching for ICP-based Camera Pose Estimation,” accepted, 2018 IEEE International Symposium on Circuits and Systems.
J.H. Ye and M.D. Shieh, 2018, April, “High-Performance NTT Architecture for Large Integer Multiplication,” accepted, 2018 IEEE International Symposium on VLSI Design, Automation & Test.
2017
.W. Chen, M.D. Shieh, J.M. Lu, H.L. Huang and Y.H. Chen, 2017, September, “Content-aware Line-based Power Modeling Methodology for Image Signal Processor,” 2017 IEEE SOC Conference (SOCC), pp. 346-350.
2016
C.W. Chen, F.K. Hsu, D.W. Yang, J. Wang and M.D. Shieh, 2016, October, “Effective Model Construction for Enhanced Prediction in Example-based Super-Resolution,” 2016 IEEE Asia Pacific Conference on Circuits and Systems, pp. 156-159.
W.J. Chen, C.W. Chen, J. Wang and M.D. Shieh, 2016, September, “Effective registration for multiple users AR system ,” 2016 IEEE International Symposium on Mixed and Augmented Reality (ISMAR), pp. 270-271.
T.Y. Lin, C.W. Chen, J. Wang and M.D. Shieh, 2016, September, “Motion-aware iterative closest point estimation for fast visual odometry,”2016 IEEE International Symposium on Mixed and Augmented Reality (ISMAR), pp. 268-269.
C.W. Chen, F.K. Hsu, D.W. Yang, J. Wang and M.D. Shieh, 2016, May, “Fast Model Searching and Combining for Example Learning-based Super-Resolution,” 2016 IEEE International Symposium on Circuits and Systems, pp. 1994-1997.
2015
D.W. Yang, Y.C. Chang, C.W. Chen, J. Wang and M.D. Shieh, 2015, October, “Low-Complexity Depth Generation Using Vanishing Cues for General Applications,” 2015 International Conference on Innovation, Communication and Engineering, pp. 1-4.
H.F. Luo, M.D. Shieh and K.H. Lee, 2015, June, “A radix-2/3/22/23 MDC architecture for variable-length FFT processors,” 2015 IEEE International Conference on Consumer Electronics - Taiwan, pp. 180-181.
H.F. Luo and M.D. Shieh, 2015, June, “Efficient memory management scheme for pipelined shared-memory FFT processors,” 2015 IEEE International Conference on Consumer Electronics - Taiwan, pp. 178-179.
C.W. Chen, C.H. Su, D.W. Yang, J. Wang, C.C. Lo and M.D. Shieh, 2015, May, “High-Quality Texture Compression Using Adaptive Color Grouping and Selection Algorithm,” 2015 IEEE International Symposium on Circuits and Systems, pp. 2760-2763.
J.S. Lin, M.D. Shieh, C.Y. Liu and D.W. Yang, 2015, April, “Efficient Highly-Parallel Turbo Decoder for 3GPP LTE-Advanced,” 2015 IEEE International Symposium on VLSI Design, Automation & Test, pp. 1-4.
2014
J.H. Ye, S.H. Huang and M.D. Shieh, 2014, June, “An Efficient Countermeasure against Power Attacks for ECC over GF(p),” 2014 IEEE International Symposium on Circuits and Systems, pp. 814-817.
Y.K. Lu, S.M. Chung and M.D. Shieh, 2014, April, “Low-complexity Architecture for Chase Soft-decision Reed-Solomon Decoding,” 2014 IEEE International Symposium on VLSI Design, Automation & Test, pp. 1-4.
D.W. Yang, L.C. Chu, C.W. Chen, J.M. Gan, J. Wang and M.D. Shieh, 2014 April, “Low Complexity Stereo Matching Algorithm Using Adaptive Sized Square Window,” 2014 IEEE International Symposium on VLSI Design, Automation & Test, pp. 1-4.
2013
J.H. Ye, T.W. Hung and M.D. Shieh, 2013, April, “Energy-efficient Architecture for Word-based Montgomery Modular Multiplication Algorithm,” 2013 IEEE International Symposium on VLSI Design, Automation & Test, pp. 1-4.
2012
D.W. Yang, C.W. Chen, C.H. Chang, Y.C. Chang, M.D. Shieh, J. Wang and C.C. Lo, 2012, December, “Face detection architecture design using hybrid skin color detection and cascade of classifiers,” 2012 Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 543-546.
S.H. Fang, J.Y. Chen, J.S. Lin, M.D. Shieh, W.C. Huang and J.Y. Hsu, 2012, December, “Blind channel estimation for MIMO-OFDM systems with repeated time-domain symbols,” 2012 Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 37-40.
D.W. Yang, J.S. Lin, S.H. Fang, C.F. Lin and M.D. Shieh, 2012, December, “High Performance Turbo-MIMO System Design with Iterative Soft-detection and Decoding,” 2012 Asia-Pacific Signal and Information Processing Association Annual Submit and Conference (APSIPA-ASC), pp. 1-4.
J.S. Lin, Y.T. Hwang, P.H. Chu, M.D. Shieh and S.H. Fang, 2012, May, “An Efficient QR Decomposition Design for MIMO Systems,” 2012 IEEE International Symposium on Circuits and Systems, pp. 1508-1511.
S.H. Wang, W.C. Lin, J.H. Ye and M.D. Shieh, 2012, May, “Fast Scalable Radix-4 Montgomery Modular Multiplier,” 2012 IEEE International Symposium Circuits and Systems, pp. 3049-3052.
W.C. Lin, J.H. Ye, D.W. Yang, S.Y. Huang, M.D. Shieh and J. Wang, 2012, May, “Efficient Scissoring Scheme for Scanline-based Rendering of 2D Vector Graphics,” 2012 IEEE International Symposium Circuits and Systems, pp. 766-769.
Y.K. Lu and M.D. Shieh, 2012, April, “Efficient Architecture for Reed-Solomon Decoder,” 2012 IEEE International Symposium on VLSI Design, Automation & Test, pp. 1-4.
S.H. Fang, J.Y. Chen, M.D. Shieh and J.S. Lin, 2012, November, “Subspace-based Blind Channel Estimation with Periodicity for OFDM Systems without Cyclic Prefix,” in Proc. 2011 IEEE Region 10 Conference (TENCON), pp. 470-473.
M.D. Shieh, S.H. Fang, S.C. Tang and D.W. Yang, 2012, September, “VLSI Design of Area-efficient Memory Access Architectures for Quasi-cyclic LDPC Codes,” in Proc. 2011 IEEE SOC Conference (SOCC), pp. 242-246.
2010
D.W. Yang, M.D. Shieh, W.H. Kuo and J.Wang, 2010, December, "Efficient Protocol Converter Generation for System Integration," 2010 Asia Pacific Conference on Circuits and Systems, pp. 903-906.
S.H. Fang, J.Y. Chen, M.D. Shieh and J.S. Lin, 2010, December, "A Signal Permutation Method for Cyclic-Prefix-Free OFDM Channel Estimation," 2010 Asia Pacific Conference on Circuits and Systems, pp. 656-659.
Y.K. Lu and M.D. Shieh, 2010, November, "Design of High-Throughput Re-Encoder for Soft-Decision Reed-Solomon Decoding," 2010 International Symposium on Next-Generation Electronics (ISNE), pp. 36-39.
J. S. Lin, S.H. Fang, M.D. Shieh and Y.H. Jen, 2010, November, "Design of High-Throughput MIMO Detectors Using Sort-Free and Early-Pruned Techniques," TENCON 2010 IEEE Region 10 Conference, pp. 1513-1516.
C. C. Lo, C.W. Hsu and M.D. Shieh, 2010, October. "Area-Efficient H.264 VLC Decoder Using Sub-tree Classification," The Sixth International Conference on Intelligent Information Hiding and Multimedia Signal Processing, pp. 284-287.
H. F. Lo, M.D. Shieh, Y.J. Liu and C.M. Wu, 2010, May, “Efficient Memory Management for FFT Processors” 2010 IEEE International Symposium on Circuits and Systems, pp. 3737-3740.
W. C. Lin, M.D. Shieh and C.M. Wu, 2010, May, “Design of High-Speed Bit-Serial Divider in GF(2m)” 2010 IEEE International Symposium on Circuits and Systems, pp. 713-716.
Y. K. Lu, M.D. Shieh and C.M. Wu, 2010, May, “Low-Complexity Reed-Solomon Decoder for Optical Communications,” 2010 IEEE International
S. H. Fang, J.Y. Chen, M.D. Shieh and J.S. Lin, 2010, May, “Subspace-Based Blind Channel Estimation for OFDM Systems with Conjugate-Symmetric Property,” in Proc. 2010 IEEE Vehicular Technology Conference, pp. 1-5.
Y. K. Lu and M.D. Shieh, 2010, April, “Low-complexity Reed-Solomon Decoder for Blu-ray Disc Applications,” 2010 IEEE International Symposium on VLSI Design, Automation & Test, pp. 359-362.
2009
J. J. Zhu, W.C. Lin, J.H. Ye and M.D. Shieh, 2009, November, “Efficient Software-based Self-test Methods for Embedded Digital Signal Processors,” The 18 th Asian Test Symposium, pp. 206-211.
C. C. Lo, J.G. Luo and M.D. Shieh, 2009, August, “Hardware/Software Co-design of Resource Constrained Real-Time Systems,” Fifth International Conference on Information Assurance and Security, vol. 1, pp. 177-180.
Y. L. Tsai, C.C. Lo, J.G. Luo and M.D. Shieh, 2009, May, “Efficient Inverse Transform design for Multi-Standard Video Coding Applications,” 2009 International Symposium on Digital Life Technologies.
W. C. Lin, M.D. Shieh and C.M. Wu, 2009, May “Flexible GF(2m) Divider Design for Cryptographic Applications,” 2009 IEEE International Symposium on Circuits and Systems, pp. 25-28.
S. H. Fang, J.Y. Chen, M.D. Shieh and J.S. Lin, 2009, May, “A Generalized Blind Channel Estimation Algorithm for OFDM Systems with Cyclic Prefix,” 2009 IEEE International Symposium on Circuits and Systems, pp. 2469-2472.
C. C. Lo, S.T. Tsai and M.D. Shieh, 2009, April, “A Reconfigurable Architecture for Entropy Decoder and IDCT in H.264,” 2009 IEEE International Symposium on VLSI Design, Automation & Test, pp. 279-282.
Y.K. Lu, M.D. Shieh and W.H. Kuo, 2009, April, “Design of High-Speed Errors-and-Erasures Reed-Solomon Decoders for Multi-Mode Applications,” 2009 IEEE International Symposium on VLSI Design, Automation & Test, pp. 199-202.
S.H. Fang, J.Y. Chen, M.D. Shieh and J.S. Lin, 2009, April “Modified Subspace-Based Channel Estimation Algorithm for OFDM Systems,” 2009 IEEE Vehicular Technology Conference, pp. 1-5.
2008
W.C. Tasi, M.D. Shieh, W.C. Lin and C.L. Wey, 2008, November, “Design of Square Generator with Small Look-up Table,” in Proc. 2008 IEEE Asia-Pacific Conference on Circuits and Systems.
W.C. Lin, J.H. Chen and M.D. Shieh, 2008, May, “A New look-up table-based multiplier/squarer design for cryptosystems over GF(2m),” 2008 IEEE International Symposium on Circuits and Systems, pp. 464-467.
J.H. Chen, W.C. Lin, H.S. Wu and M.D. Shieh, 2008, May, “High-Speed Modular Multiplication Design for Public-key Cryptosystems," 2008 IEEE International Symposium on Circuits and Systems, pp. 680-683.
J.H. Chen, S.J. Huang, W.C. Lin, Y.K. Lu and M.D. Shieh, 2008, July, “Exploration of Low-Cost Configurable S-Box Designs for AES Applications,” in Proc. The Fifth International Conference on Embedded Software and Systems, pp. 422-428.
2007
C.C. Lo, Y.J. Zeng and M.D. Shieh, 2007, October, “Design and Test of A High-Throughput CABAC Encoder,” TENCON 2007 IEEE Region 10 Conference.
W.C. Lin, M.D. Shieh, J.H. Chen, C.M. Wu and H.S. Wu, 2007, October, “A Combined Multiplication/Division Algorithm for Cost-Effective Design of Elliptic Curve Cryptosystem over GF(2m),” TENCON 2007 IEEE Region 10 Conference.
J.H. Chen, H.S. Wu, M.D. Shieh and W.C. Lin, 2007, May, “A New Montgomery Modular Multiplication Algorithm and its VLSI Design for RSA Cryptosystem,” 2007 IEEE International Symposium on Circuits and Systems, pp. 3780-3783.
2006
J.H. Chen, M.D. Shieh, H.S. Wu and W.C. Lin, 2006, December, “Asynchronous Design of Modular Multiplication Using Adaptive Radix Computation,” 2006 IEEE Asia-Pacific Conference on Circuits and Systems, pp. 607-610.
M.D. Shieh, Y.K. Lu, S.M. Chung and J.H. Chen, 2006, May, “Design and Implementation of Efficient Reed-Solomon Decoders for Multi-Mode Applications,” 2006 IEEE International Symposium on Circuits and Systems, pp. 289-292.
M.D. Shieh, T.P. Wang, C.M. Wu and C.M. Huang, 2006 May, “Efficient Path Metric Access for Reducing Interconnect Overhead in Viterbi Decoders,” 2006 IEEE International Symposium on Circuits and Systems, pp. 4815-4818.
J.S. Lin, C.K. Lee, M.D. Shieh and J.H. Chen, 2006 May, “High-Speed CRC Design for 10 Gbps Applications,” 2006 IEEE International Symposium on Circuits and Systems, pp. 3177-3180.
2005
J.H. Chen, M.D. Shieh and C.M. Wu, 2005, May, “Concurrent Algorithm for High-Speed Point Multiplication in Elliptic Curve Cryptography,” 2005 IEEE International Symposium on Circuits and Systems, pp. 5254-5257.
T.P. Wang, C.Y. Tsai, M.D. Shieh, and K.J. Lee, 2005, April, “Efficient Test Scheduling for Hierarchical Core Based Design,” IEEE VLSI-TSA International Symposium on VLSI Design, Automation & Test, pp. 200-205.
2004
J.H. Chen, M.D. Shieh, and C.M. Wu, 2004, December, “High-Speed VLSI Design for Montgomery Inverse over GF(2m),” 2004 IEEE Asia-Pacific Conference on Circuits and Systems, pp. 25-28.
M.D. Shieh, S.C. Shen, Y.C. Lin and K.J. Lee, 2004, December, “Efficient Testing and Design-for-Testability Schemes for Multimedia Cores: A Case Study on DCT Circuits,” 2004 IEEE Asia-Pacific Conference on Circuits and Systems, pp. 177-180.
C.M. Wu, M.D. Shieh, C.H. Wu, Y.T. Hwang, J.H. Chen and H.F. Lo, 2004, May, “VLSI Architecture Exploration for Sliding-Window Log-MAP Decoders,” 2004 IEEE International Symposium on Circuits and Systems, pp. 513-516.
2003
C.M. Wu, M.D. Shieh, H.F. Lo and M.H. Hu, 2003, May, “Implementation of Channel Demodulator for DAB Systems,” 2003 IEEE International Symposium on Circuits and Systems, vol. 2, pp.25-28.
2002
C.M. Wu, M.D. Shieh and C.H. Wu, 2002, August, “Memory Arrangements in Turbo Decoders Using Sliding-Window MAP Algorithm,” 2002 IEEE International Symposium on Circuits and Systems, pp. V-557-560.
C.H. Wu, C.M. Wu, M.D. Shieh and Y.T. Hwang, 2002, August, “An Area-Efficient Systolic Division Circuit over GF(2m) for Secure Communication,” 2002 IEEE International Symposium on Circuits and Systems, pp. V-733-736.
2001
C.M. Wu, M.D. Shieh, C.H. Wu and M.H. Sheu, 2001, May, “VLSI Architecture of Extended In-Place Path Metric Update for Viterbi Decoders,” 2001 IEEE International Symposium on Circuits and Systems, pp. 206-209.
H.F. Lo, M.D. Shieh and C.M. Wu, 2001, May, “Design of an Efficient FFT Processor for DAB System,” 2001 IEEE International Symposium on Circuits and Systems, pp. 654-657.
C.H. Wu, C.M. Wu, M.D. Shieh and Y.T. Hwang, 2001, May, “Systolic VLSI Realization of a Novel Iterative Division Algorithm over GF(2m): a High-Speed, Low-Complexity Design,” 2001 IEEE International Symposium on Circuits and Systems, pp. 33-36.
2000
M.D. Shieh, H.F. Lo and M.H. Sheu, 2000, December “High-Speed Generation of LFSR Signatures,” The 9th Asian Test Symposium, pp.222-227.
M.D. Shieh, C.H. Wu, M.H. Sheu, J.L. Sheu and C.H. Wu, 2000, August, “Asynchronous Implementation of Modular Exponentiation for RSA Cryptography,” The Second IEEE Asia Pacific Conference on ASICs, pp. 191-194.
C. H. Wu, C.M. Wu, M.D. Shieh and Y.T. Hwang, 2000, August, “Novel Iterative Division Algorithm over GF(2m) and Its Semi-Systolic VLSI Realization,” IEEE Midwest Symposium on Circuits and Systems, pp. 280-283.
C.M. Wu, M.D. Shieh, C.H. Wu and M.H. Sheu, 2000, May, “An Efficient Approach for In-Place Scheduling of Path Metric Update in Viterbi Decoder,” 2000 IEEE International Symposium on Circuits and Systems, pp. III-61~III-64.
1999
M.H. Sheu, S.C. Tsai and M.D. Shieh, 1999, August, “A New Algorithm and VLSI Architecture Design for Lossless Coding of VQ Codevector Index,” The First IEEE Asia Pacific Conference on ASICs.
M.D. Shieh, C.M. Wu, H.H. Chou, M.H. Chen and C.L. Liu, 1999, June, “Design and Implementation of a DAB Channel Decoder,” 1999 IEEE International Conference on Consumer Electronics, pp. 74-75.
M.D. Shieh, C.H. Wu, M.H. Sheu, C.H. Wu and J.L. Sheu, 1999, June, “A VLSI Architecture of Fast High-Radix Modular Multiplication for RSA Cryptosystem,” 1999 IEEE International Symposium on Circuits and Systems, pp. I-500-I-503.
J.C. Huang, C.M. Wu, M.D. Shieh and C.H. Wu, 1999, June, “An Area-Efficient Versatile Reed-Solomon Decoder for ADSL,” 1999 IEEE International
1998
M.H. Sheu, C.H. Chen, M.D. Shieh and T.S. Li, 1998, June, “A High Performance VLSI Architecture Design for 10/100M bps Ethernet Switching Fabric,” 1998 IEEE International Conference on Consumer Electronics, pp. 26-27.
C.H. Chen, M.H. Sheu, M.D. Shieh, T.S. Li and M.T. Chen, ”Design and Implementation of 10/100 Mbps Ethernet Switching Hub Controller,” IEEE Asia Pacific Conference on Communications, 1998.
J.L. Sheu, M.D. Shieh, C.H. Wu and M.H. Sheu, 1998, June, “A Pipelined Architecture of Fast Modular Multiplication for RSA Cryptography,” 1998 IEEE International Symposium on Circuits and Systems, pp. II-121-II-124.
M.D. Shieh, M.H. Sheu, C.M. Wu and W.S. Ju, 1998, June, “Efficient Management of In-Place Path Metric Update and its Implementation for Viterbi Decoder,” 1998 IEEE International Symposium on Circuits and Systems, pp. IV-449-IV-452.
M.H. Sheu, M.D. Shieh and S.W. Liu, 1998, June, “A VLSI Architecture Design with Lower Hardware Cost and Less Memory for Separable 2-D Wavelet Transform,” 1998 IEEE International Symposium on Circuits and Systems, pp. V-457-V-460.
1997
C.H. Wu, M.D. Shieh, M.R. Wang and J.S. Wang, 1997, October, “A Versatile Multimedia Codec System Based on the TMS320C80 Digital Signal Processor,” 1997 Workshop on Consumer Electronics: Digital Video and Multimedia, pp. B4-2/6-B4-2/11.
W.S. Ju, M.D. Shieh and M.H. Sheu, 1997, August, “A Low-Power VLSI Architecture for the Viterbi Decoder,” 1997 Midwest Symposium on Circuits and Systems, pp.1201~1204.
M.D. Shieh, M.H. Sheu and Y.C. Hsu, 1997, August, “A High-Performance VLSI Architecture for MAPS Criterion Motion Estimation,” 1997 Midwest Symposium on Circuits and Systems, pp. 1221~1224.
M.H. Sheu, M.D. Shieh and S.W. Liu, 1997, August, “A Low-Cost VLSI Architecture Design for Non-separable 2-D Discrete Wavelet Transform,” 1997 Midwest Symposium on Circuits and Systems, pp. 1217~1220.
M.H. Sheu, M.D. Shieh, S.W. Liu and C. Dou, 1997, August, “An Efficient Hardware Design Approach from System-Level Specification,” 1997 Midwest Symposium on Circuits and Systems, pp. 1213~1216.
M.R. Wang, J.S. Wang, Y.T. Huang, M.H. Sheu and M.D. Shieh, 1997, September, “A Versatile Signal Processing Board for Real-Time Multimedia Communication,” 7th International Symposium on IC Technology, Systems & Applications, pp. 331-334.
Y.S. Ke, M.D. Shieh and M.H. Sheu, 1997, September, “On the Implementation of Wave-Pipelined Multipliers in Lookup Table-Based FPGAs,” 7th International Symposium on IC Technology, Systems & Applications, pp. 434-437.
M.D. Shieh, M.H. Sheu, H.R. Wang and H.C. Cheng, 1997, September, “Dichotomy-Based Constrained Encoding for Low Switching Activity in Asynchronous Finite State Machines,” 7th International Symposium on IC Technology, Systems & Applications, pp. 509-512.
C. Dou, M.H. Sheu and M.D. Shieh, 1997, “Performance Evaluation for HW/SW Codesign of Communication Protocols,” 1997 Asia-Pacific Conference on Hardware Description Language.
1996
C. Dou and M.D. Shieh, 1996, October, “A CAM-Based VLSI Architecture for Shared Buffer ATM Switch with Fuzzy Controlled Buffer Management,” 1996 IEEE International Conference on Computer Design, pp.149-152.
M.D. Shieh, M.H. Sheu and W.S. Ju, 1996, August, “Low-Power State Assignment for Asynchronous Finite State Machines,” 1996 Midwest Symposium on Circuits and Systems, pp.1325-1328.
M.D. Shieh, M.H. Sheu and Y.C. Hsu, 1996, August, “MAPS: A New and Efficient Block-Matching Criterion for Motion Estimation,” 1996 Midwest Symposium on Circuits and Systems, pp.1393-1396.
M.H. Sheu, M.D. Shieh and S.F. Cheng, 1996, August, “A Unified VLSI Architecture for Decomposition and Synthesis of Discrete Wavelet Transform,” 1996 Midwest Symposium on Circuits and Systems, pp. 113-116.
M.D. Shieh, J.M. Hong and M.H. Sheu, 1996, May, “A CAD System for Automatic Synthesis of Generalized Asynchronous Circuits,” 1996 IEEE International Symposium on Circuits and Systems, vol. 4, pp. 818-821.
M.H. Sheu, S.F. Cheng and M.D. Shieh, 1996, May, “A Pipelined VLSI with Module Structure Design for Discrete Wavelet Transforms,” 1996 International Sysmpium on Circuits and Systems, Vol. 4, pp. 352-355.
1993
C.L. Wey, M.D. Shieh and P.D. Fisher, 1993, October, “ASLCScan: A Scan Design Technique for Asynchronous Sequential Logic Circuits,” IEEE International Conference on Computer Design, pp. 159-162.
1993, August, “Scan Design for Asynchronous Sequential Logic Circuits Using SR-Latches,” 36th Midwest Symposium on Circuits and Systems, pp. 1300-1303.
1992
M.D. Shieh, C.L. Wey and P.D. Fisher, 1992, August, “Model of Asynchronous Finite State Machines and Their Pipelined Structures,” 35th Midwest Symposium on Circuits and Systems, pp. 659-662.
1991
C.L. Wey, M.D. Shieh and P.D. Fisher, 1991, November, “On Synthesis for Testability in Asynchronous Sequential Logic Circuits,” presented at IFIP Workshop on the Relationship Between Synthesis, Test, and Verification, Berkeley.